ASML Aims for Hyper-NA EUV, Shrinking Chip Limits (eetimes.com) | HN Screenshots

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Screenshot of eetimes.com: ASML Aims for Hyper-NA EUV, Shrinking Chip Limits

First screen, captured 2 years ago.

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Screenshot of eetimes.com: Nvidia Trains LLM on Chip Design

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Screenshot of eetimes.com: Tenstorrent engineers talk open-sourced bare-metal stack

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Screenshot of eetimes.com: RISC-V Is Inevitable: State of the Union Keynote Argues

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Screenshot of eetimes.com: ZeroRISC Gets $10M Funding, Says Open-Source Silicon Security Inevitable

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34 points by wslh 1 year ago | 4 comments

Screenshot of eetimes.com: Pulsed laser deposition at wafer level is a game changer

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53 points by jnord 2 years ago | 6 comments

Screenshot of eetimes.com: RISC-V in AI and HPC Part 1: Per Aspera Ad Astra?

RISC-V in AI and HPC Part 1: Per Aspera Ad Astra?(eetimes.com)

20 points by fork-bomber 1 year ago | 2 comments