First screen, captured 1 day ago. Hover to scroll the page, or open the video.

It's the memory latency, stupid

What HN thinks

A support group for people whose benchmarks were dismissed as premature optimization.

Mechanical sympathy is a lost art
Commenters share stories of large speedups from cache-friendly layouts, index+generation handles and fixing access patterns, lamenting that few developers understand hardware anymore.
Clean Code culture resists optimization
Some blame aesthetic dogma like Clean Code and misquoted Knuth for pushback against performance work, while others defend it as a trade-off or note change risk.
Engine homogenisation debate
A tangent argues whether consolidation around Unreal, Unity and Godot erodes low-level skills or is simply sensible commodification.

Consensus: Most agree memory access patterns dominate real-world performance and that cache-aware design often yields large wins for modest effort, though the article's technique itself isn't novel.

Recommended in the comments

What Every Programmer Should Know About Memory ↗ (book): Posted as the classic reference on the topic, with a wish for a 2026 update.
DuckDB (tool): Cited as an existing engine that already does efficient aggregation.
ClickHouse (tool): Cited alongside DuckDB as making such projects redundant.
Zig (tool): Explicit allocators make developers feel the cost of allocations.

Summarised by Claude from the comment thread 1 day ago.

Points: 238
Comments: 76
Best rank: #3
Posted: 2026-10-31 by ntur1337
Category: Data databases

cpu-caches memory-latency group-by radix-partitioning rust query-engines performance-engineering perf

All captures:

Full page

Captured 1 day ago. Click for the whole screenshot.

Looks similar

Screenshot of divagr.com: Qwenputer: A functioning, deterministic RISC-V CPU inside Qwen3.5

Qwenputer: A functioning, deterministic RISC-V CPU inside Qwen3.5 (divagr.com)

666 points by csmantle 4 days ago | 140 comments

Blog post describing Qwenputer, a Qwen3.5 4B model with a RISC-V CPU compiled into its weights that uses Gated DeltaNet layers as RAM to run code internally.

qwen risc-v gated-deltanet compiled-weights